Flash Electrically Erasable and Programmable ROMs (shortly, Flash EEPROMs) have memory cells which are formed by floating-gate MOSFETs. A Flash EEPROM memory cell is written by means of hot-electron injection into the floating gate, and is erased by means of Fowler-Nordheim tunneling of electrons through the oxide layer interposed between the floating gate and the semiconductor substrate.
To activate the tunnel effect, a sufficiently high electric field must be present in the oxide layer. This is normally achieved by applying a suitable electric potential difference between the source electrode and the control gate electrode of the memory cell, while the drain electrode is normally left floating.
According to a known technique, such a potential difference is developed by biasing the source electrode of the floating-gate MOSFET with a high positive voltage of the order of 12 V, and keeping the control gate electrode grounded.
In Dual Power Supply (DPS) memories the 12 V voltage is supplied by an external power supply, provided in addition to the 5 V (or 3 V) power supply. As an alternative, the 12 V voltage could be generated directly on-chip by suitable charge pumps which, starting from the available 5 V voltage, boost it to the required high voltage. Memory devices of this kind are called Single Power Supply (SPS), since they only require one external power supply (namely, the 5 V one).
The above-mentioned technique for erasing memory cells has however a number of drawbacks, mainly related to the high reverse bias condition of the PN junction formed by the source electrode and the substrate (normally at the ground potential). One significant drawback occurs when a memory cell is biased to be erased, a current of the order of 10 nA starts flowing due to band-to-band tunneling. Since in Flash EEPROMs several memory cells (sometimes all of them) can be erased simultaneously, the individual currents sum up to values of some tens of milliamperes in memories with size of the order of some megabits.
If on the one hand this is not a major problem in DPS memories, wherein the 12 V external power supply is able to provide the required current, on the other hand the high current consumption during erasure makes it impossible to use on-chip charge pumps to generate the 12 V voltage.
In the U.S. Pat. No. 5,077,691 a Flash EEPROM array with negative gate voltage erase operation is proposed which provides for erasing a Flash EEPROM memory cell by applying a relatively high negative voltage (-12 V to -17 V) to the control gate electrode of the cell, and a low positive voltage (+0.5 V to +5 V) to the source electrode.
In this way, the source electrode bias voltage can be derived from the 5 V external supply, and the negative voltage for the control gate can be generated directly on-chip by means of charge pumps.
When such a solution is adopted, it is however necessary to provide a suitable regulation for the on-chip generated negative voltage.
The U.S. Pat. No. 5,282,170 describes a negative power supply circuit for a SPS Flash EEPROM implementing said negative gate voltage erase operation. The negative power supply circuit comprises charge pumps for generating a high negative voltage to be supplied to word lines of the memory array during flash erasure of the memory cells, and a regulation circuit for regulating the negative voltage generated by the charge pumps, so that it is independent of the external 5 V supply.
The regulation circuit comprises a comparator with the inverting input supplied with a reference voltage derived by resistive partition from the external supply. The non-inverting input is connected to the central node of a capacitive divider connected between ground and a sensing node in turn coupled to the negative voltage to be regulated (i.e., to the outputs of the charge pumps) via a pair of diode-connected P-channel MOSFETs. The output of the comparator controls the gate electrode of a pull-up P-channel MOSFET connected to the external supply and coupled to the sensing node via a further diode-connected P-channel MOSFET. During an initialization phase, the two capacitors of the capacitive divider are charged up to a voltage of about 2 V, and the sensing node is grounded. After the initialization phase, the comparator compares the voltage at the central point of the capacitive divider with said reference voltage and, if the former is lower than the latter, turns the pull-up MOSFET on: in this way, the load current of the charge pumps is increased, and the voltage on the word lines decreases in absolute value.
A problem of the regulation circuit described above resides in that the potential on the sensing node is affected by the voltage drop across said pair of diode-connected P-channel MOSFETs, due to the current flowing through them during the regulation of the negative voltage. This means that the voltage compared by the comparator with the reference voltage does not exactly correspond to the voltage to be regulated.